Presented is the complete functional model of pipelining in FPGA based Canny. Distinguished are high-, mid- and low level of pipelining. The speed capabilities of pipelining in Gaussian filtering, Sobel, gradient magnitude and direction, non-maximum suppression are studied at each level. Provided are the formulae for calculating the exact number of clock cycles required to execute these Canny modules with respect to the two input variables: image size and Gaussian filter size. Proved is the upper limit of FPGA based Canny speed in terms of pipelining.