Parallelism in speed focused FPGA based Canny computations

Abstract

Presented is a complete functional model of parallelism in FPGA based Canny computations. Distinguished are top-, high-, mid- and low level of parallelism. The specific  use of each level in tthe different parts of Canny algorithm is thoroughly explored. Studied is the impact of all levels of parallelism on speed on the basis of particular formulae. The mathematics and speed capabilities of a specific type of FPGA based multiplication is analyzed in the context of parallelism.