Addition is a fundamental integer arithmetic operation in digital image processing. Ultimate execution speed of FPGA based edge detection which uses Gaussian filtering has two parameters: maximum operating frequency and minimum number of clock cycles required to obtain mathematically accurate result. The computational specifics of weighed average function define adding a number of addends in parallel as critical to the concept of achieving ultimate execution speed of FPGA based edge detection. This paper is focused on exploring the capabilities of parallel addition to contribute to the goal of securing a Gaussian filtered pixel every single clock cycle at the maximum operating frequency. Ten Intel (Altera) FPGA families are used in the explorations.