The goal of ultimate execution speed in FPGA based edge detection which uses Gaussian filtering requires defining the values of maximum operating frequency and minimum number of clock cycles taken to secure mathematically accurate result. A critical component in achieving that goal is the simultaneous addition of convolution results calculated by the weighted average function in the process of filtering an input image pixel. The paper studies the capabilities of different addition algorithms to be used in FPGA based edge detection for simultaneous addition of convolution results in terms of guaranteeing minimum number of clock cycles for various Gaussian filter sizes at the maximum operating frequency. On that basis, analyzed is the impact of simultaneous addition of convolution results on the organization of computations in the Gaussian filtering module of FPGA based edge detection. Ten Intel (Altera) FPGA families are used in conducting the explorations.